module calc_tb();
//------------------------------------------------------
//  Clock and reset
reg CLK;           
reg RST;

initial CLK <= 0;
always #50 CLK <= ~CLK; 
    
initial
    begin
        RST <= 1;      
        RST <= #500 0;
    end  
//------------------------------------------------------
// calculator interface signals
wire        opc_stb_i;
wire [ 7:0] opc_i;
wire        data_stb_i;  
wire [31:0] dat_i; 
wire        ack_i; 
                  
wire [31:0] result;     
wire        result_stb; 
wire        result_ack;         
//------------------------------------------------------
//  buffer for operation and data
//  bit 31- 0: data 
//  bit 32   : data stb
//  bit 40-33: operation
//  bit 41   : data     
//------------------------------------------------------
reg  [41:0] input_data [0:10]; // buffer for 11 operations   
reg  [ 7:0] op_ptr;            // pointer to next operation/data
wire [41:0] curr_input_data;   // pointed next operation/data
//------------------------------------------------------
// operation opcodes (8bit):
//  1 - '+'
//  2 - '-'      
//  4 - '*'     
//  8 - '='
//------------------------------------------------------
// example equation:
// result = ((1 + 12) + 354332) * 4223 - 1496398915       
//------------------------------------------------------
always@(posedge CLK or posedge RST)
    if(RST)
        begin              // OpcStb|  Opc  |DatStb |  Data
           input_data [ 0] <= {1'b0,   8'd0, 1'b1,    32'd4223      };// data 4223
           input_data [ 1] <= {1'b0,   8'd0, 1'b1,    32'd12        };// data 12
           input_data [ 2] <= {1'b0,   8'd0, 1'b1,    32'd1         };// data 1
           input_data [ 3] <= {1'b1,   8'd1, 1'b0,    32'd0         };// operation '+'
           input_data [ 4] <= {1'b0,   8'd0, 1'b1,    32'd354332    };// data 354332 
           input_data [ 5] <= {1'b1,   8'd1, 1'b0,    32'd0         };// operation '+'
           input_data [ 6] <= {1'b1,   8'd4, 1'b0,    32'd0         };// operation '*'
           input_data [ 7] <= {1'b0,   8'd0, 1'b1,    32'd1496398915};// data 1496398915 
           input_data [ 8] <= {1'b1,   8'd2, 1'b0,    32'd0         };// operation '-'  
           input_data [ 8] <= {1'b1,   8'd8, 1'b0,    32'd0         };// operation '='
           input_data [10] <= {1'b0,   8'd0, 1'b0,    32'd0         };// no operation, no data 
        end 
//------------------------------------------------------
always@(posedge CLK or posedge RST)                              
     if(RST)             op_ptr  <=                8'd0; 
else if(ack_i)           op_ptr  <=       op_ptr + 8'd1;   
//------------------------------------------------------ 
assign curr_input_data = input_data[op_ptr];   
//------------------------------------------------------ 
assign  opc_stb_i   =  curr_input_data[41]; 
assign  opc_i       =  curr_input_data[40:33];  
assign  data_stb_i  =  curr_input_data[32];   
assign  dat_i       =  curr_input_data[31: 0];             
//------------------------------------------------------
// Calculator instantion
calc calc_instcalc // put your's calc module name here
(
.CLK        (CLK),
.RST        (RST),
                   
.OPC_STB_I  (opc_stb_i),
.OPC_I      (opc_i), 
.DAT_STB_I  (data_stb_i), 
.DAT_I      (dat_i), 
.ACK_I      (ack_i), 
                  
.DAT_O      (result),
.STB_O      (result_stb),
.ACK_O      (result_ack)
);                     
//------------------------------------------------------
assign result_ack = result_stb;
//------------------------------------------------------
endmodule